kontakt (at) tomaszmazurkiewicz.pl

FPGA

5+ years of experience in FPGA development, mainly implementing cryptographic algorithms.

Crypto

Degree in Information Technology with a specialization in Cryptology, 10+ years of experience in teams working on Crypto.

Python

5+ years of experience in software implementations using Python.

PM | Leadership

3+ years of experience working as Team Leader and Project Manager.

PhD

Degree in Information and Communication Technology, obtained based on my work on logic synthesis and its application in FPGA-based electronic devices.

R&D

Experience working in several projects concerning R&D solutions, e.g. the National Center for Research and Development projects.

About Me

I received my M.Sc. degree in Information Technology with a specialization in cryptology from the Military University of Technology, Warsaw, Poland, in 2014. I received a PhD. Eng. degree in Information and Communication Technology in 2021 from the same University. My research interests are in logic synthesis and its application in FPGA-based electronic devices. My recent activities cover minimization methods of specific Boolean functions (called index generation functions), i.e., linear and non-disjoint functional decomposition. I am an author or co-author of several papers dealing with this topic, presented at international conferences such as FedCSIS, ICSEng, MIXDES, and ISMVL.

I gained professional experience in institutions dealing with cybersecurity and hardware security, mainly in interdisciplinary teams (IT and electronics). Currently, I work as a team leader and project manager. I am also an expert in some research and development projects concerning electronic devices used to provide security.

Area of expertise

Hardware, Python, Research, FPGA, Programming, Logic synthesis, Digital electronics, Agile, Electronics, Project Management, Boolean algebra, Cryptography, IT, Prince 2, Research, Team leadership, Verilog, IntelFPGA, Security, LaTeX, FCE, VHDL

Research

My research interests are in logic synthesis and its application in FPGA-based electronic devices. My recent activities cover minimization methods of specific Boolean functions called index generation functions. I also work on the generalization of proposed algorithms. I am an author or co-author of several papers dealing with this topic.

International conferences:

- Mazurkiewicz T., 2023. XOR-based decomposition and its application in memory-based and reversible logic synthesis, 18th Conference on Computer Science and Intelligence Systems (FedCSIS), Warsaw, Poland;
- Mazurkiewicz T., 2022. Approximate memory-based logic synthesis of index generation functions using linear decomposition, 52nd IEEE International Symposium on Multiple-Valued Logic (ISMVL), Dallas, USA, pp. 145-150;
- Mazurkiewicz T., 2021. Reducing compound degree for optimum linear decomposition of symmetric Index Generation Function, 28th International Conference on Systems Engineering (ICSEng), Wrocław, Poland, p. 1-10;
- Mazurkiewicz T., 2020. On Heuristic Linear Decomposition of Symmetric Index Generation Functions, 36th International Business Information Management Association (IBIMA) Conference, Granada, Spain, p. 11011 - 11018;
- Mazurkiewicz T., 2020. Non-disjoint functional decomposition of index generation functions, 50th IEEE International Symposium on Multiple-Valued Logic (ISMVL), Miyazaki, Japan, p. 137-141;
- Mazurkiewicz T., 2019. Computationally efficient index generation unit using a Bloom filter, Photonics Application in Astronomy, Communications, Industry, and High-Energy Physics Experiments (Proceedings Volume), Proc. SPIE, Wilga, Poland, p. 111761L;
- Mazurkiewicz T. and Łuba T., 2019. Linear and non-linear decomposition of index generation functions, 26th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES), Rzeszów, Poland, p. 246-251;
- Mazurkiewicz T. and Łuba T., 2019. Non-disjoint decomposition using r-admissibility and graph coloring and its application in index generation functions minimization, 26th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES), Rzeszów, Poland, p. 252-256;
- Mazurkiewicz T., Borowik G. and Łuba T., 2018. Construction of index generation unit using probabilistic data structures, 26th International Conference on Systems Engineering (ICSEng), Sydney, Australia, p. 1-7.

Polish conferences:

- Mazurkiewicz T. and Łuba T., 2018. Metody wyboru dekompozycji dla algorytmu z wykorzystaniem zbiorów niezgodnosci i ich wpływ na minimalizację generatorów indeksów, Krajowe Sympozjum Telekomunikacji i Teleinformatyki (KSTiT), in: Przegląd Telekomunikacyjny - Wiadomości Telekomunikacyjne, 8-9, p. 722-725;
- Mazurkiewicz T. and Łuba T., 2017. Redukcja Liczby Zmiennych do Reprezentacji Funkcji Generowania Indeksów, Krajowe Sympozjum Telekomunikacji i Teleinformatyki (KSTiT), w: Przegląd Telekomunikacyjny - Wiadomości Telekomunikacyjne, 8-9, p. 795-798.

Journals:

- Mazurkiewicz T., 2021. Synteza logiczna – aktualne trendy i perspektywy, Przegląd Telekomunikacyjny - Wiadomości Telekomunikacyjne, 3, s. 88-92;
- Mazurkiewicz T., 2021. Heuristic Minimization of Symmetric Index Generation Functions utilizing their Properties, Journal of Software and Systems Development 2021;
- Mazurkiewicz T., 2020. Application of graph theory algorithms in the non-disjoint functional decomposition of specific Boolean functions, Journal of Telecommunications and Information Technology, p. 67-74, 3/2020;
- Mazurkiewicz T., 2019. Realizacja sprzętowego generatora indeksów z wykorzystaniem filtru Blooma, Przegląd Telekomunikacyjny - Wiadomości Telekomunikacyjne, 3, p. 61-66;
- Łuba T. and Mazurkiewicz T., 2019. Dekompozycja funkcjonalna w syntezie funkcji generowania indeksów, Przegląd Telekomunikacyjny - Wiadomości Telekomunikacyjne, 1, p. 19-25;
- Łuba T. and Mazurkiewicz T., 2018. Synteza generatorów indeksów metodami dekompozycji liniowej i funkcjonalnej, Przegląd Telekomunikacyjny - Wiadomości Telekomunikacyjne, 5, p. 122-128;
- Mazurkiewicz T., 2017. An efficient hardware implementation of a combinations generator, Technical Sciences / University of Warmia and Mazury in Olsztyn, 20(4), p. 405-413;
- Mazurkiewicz T. and Rawski M., 2016. Przegląd algorytmów kryptograficznych pod względem realizacji sprzętowego koprocesora do zastosowań mobilnych, Przegląd Telekomunikacyjny - Wiadomości Telekomunikacyjne, 11.

Chapters:

- Mazurkiewicz T. and Ferenc D., 2017. Aspekt bezpieczeństwa we współczesnych urządzeniach elektronicznych, Cywilizacja XXI w. - nowe rozwiązania technologiczne;
- Mazurkiewicz T. and Ferenc D., 2016. Zastosowanie układów FPGA w kryptologii, Prace Seminarium Naukowego Instytutu Telekomunikacji Politechniki Warszawskiej. Działalność naukowa 2015/2016. Tom 2.

Others:

- Mazurkiewicz T., 2021. On memory-based logic synthesis of index generation functions.
- Mazurkiewicz T., 2021. Synteza logiczna funkcji boolowskich szczególnej postaci, rozprawa doktorska.
- Mazurkiewicz T., 2020. Rozwiązania typu fault-tolerance w urządzeniach kryptograficznych wykorzystujących układy programowalne.


Details about all papers and full-texts of selected papers are available on Researchgate.